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Summary of Arria V Features
Advantage
Lowest system cost
Supporting Feature
? Requires as few as four power supplies to operate
AV-51001
2013.12.26
? Available in thermal composite flip chip ball-grid array (BGA)
packaging
? Includes innovative features such as Configuration via Protocol
(CvP), partial reconfiguration, and design security
Summary of Arria V Features
Table 2: Summary of Features for Arria V Devices
Feature
Technology
Packaging
Description
? TSMC's 28-nm process technology:
? Arria V GX, GT, SX, and ST — 28-nm low power (28LP) process
? Arria V GZ — 28-nm high performance (28HP) process
? Lowest static power in its class (less than 1.2 W for 500K logic elements (LEs)
at 85°C junction under typical conditions)
? 0.85 V, 1.1 V, or 1.15 V core nominal voltage
? Thermal composite flip chip BGA packaging
? Multiple device densities with identical package footprints for seamless
migration between different device densities
? Leaded (1) , lead-free (Pb-free), and RoHS-compliant options
High-performance FPGA fabric ? Enhanced 8-input ALM with four registers
? Improved routing architecture to reduce congestion and improve compilation
time
Internal memory blocks
? M10K — 10-kilobits (Kb) memory blocks with soft error correction code
(ECC) (Arria V GX, GT, SX, and ST devices only)
? M20K — 20-Kb memory blocks with hard ECC (Arria V GZ devices only)
? Memory logic array block (MLAB)-640-bit distributed LUTRAM where you
can use up to 50% of the ALMs as MLAB memory
(1)
Contact Altera for availability.
Altera Corporation
Arria V Device Overview
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